Currently, for chip assemblies, the semiconductor industry has been utilizing solder-bumped flip-chip technology, such as “C4” (controlled-collapse chip connection), wherein solder bumps are formed on a solder-wettable terminal on the chip or die (i.e., wafer bumping) on a die pad which corresponds to a package solder element formed on a solder-wettable terminal on the package substrate (i.e., substrate preparation). The solder joints are formed by reflowing the package solder element onto the solder bump, wherein the other remaining elements of the assembly are subjected to the same heated environment as the package substrate. The chip or die and the substrate, being formed from different materials, are mismatched by their respective coefficients of thermal expansion. This being so, the solder bump is usually misaligned while reflowing the package solder element in forming the solder joints in the related art assemblies as the package substrate tends to expand at a rate greater than does the chip, thereby compromising their structural integrity, and thereby unduly limiting their electrical and thermal throughput.
FIG. 1A is a cross-sectional view of a flip-chip assembly 100, comprising: a die 5 having a plurality of die pads 6 thereon formed with a design die pad pitch value (i.e., manufacturer's value) ad; a package substrate 7 having a plurality of substrate pads 8 thereon formed with a design substrate pad pitch value (i.e., manufacturer's value) as to match the design die pad pitch value ad (i.e., as=ad); a corresponding plurality of solder bumps 10 formed on the plurality of die pads 6; and a corresponding plurality of package solder elements 9 formed on the plurality of substrate pads 8, wherein the plurality of solder bumps 10 are disposed over the corresponding plurality of package solder elements 9, prior to a reflow process (i.e, a flip-chip attachment process), in accordance with the prior art.
FIG. 1B is a cross-sectional view of the flip-chip assembly 100, as shown in FIG. 1A, comprising: a die 5 having a plurality of die pads 6 thereon formed with a thermally expanded and partially contracted die pad pitch value ad′; a package substrate 7 having a plurality of substrate pads 8 thereon formed with a thermally expanded and partially contracted substrate pad pitch value as′ which no longer matches the design substrate pad pitch value as1 the design die pad pitch value ad, nor the thermally expanded and partially contracted die pad pitch value ad′ (i.e., as′≠as≠ad≠ad′); a corresponding plurality of solder bumps 10 formed on the plurality of die pads 6; and a corresponding plurality of package solder elements 9 formed on the plurality of substrate pads 8, wherein the plurality of solder bumps 10 are disposed over the corresponding plurality of package solder elements 9, and wherein the plurality of package solder elements 9 have been reflowed onto the corresponding plurality of solder bumps 10, thereby inducing thermal stress in the assembly 100, in accordance with the prior art.
Referring to prior art FIGS. 1C and 1D, the plurality of die pads 6 and the plurality of substrate pads 8 expand at different rates, due to their respective and distinct coefficients of thermal expansion (CTE), upon exposure to heat at the reflow temperature during the flip-chip attachment process. The plurality of package solder elements 9 melt and form both the electrical and the structural connections between the plurality of substrate pads 8 and the plurality of die pads 6, wherein the plurality of die pads 6 tend to become misaligned with the plurality of substrate pads 8 due to a heat-induced “offset.” After reflow attachment, the assembly 100 is cooled, whereby the substrate 7 both thermally expands (swells) and contracts (shrinks) at a rate different from that of the die 5 due to their mismatched CTE, wherein an undesirable condition of inchoate thermogeometric hysteresis is induced. In essence, neither the plurality of substrate pads 8 nor the plurality of die pads 6 fully return to their original design pitch values (i.e., manufacturer's value), but retain some new pitch value causing significant misalignment.
Further, at some critical temperature (i.e., an equilibrium temperature Te), the substrate 7 and the die 5 are sufficiently attached so that no additional changes in pitch will occur as the assembly 100 is cooled below Te. Internal stress which is induced from the cooling of the assembly 100 below the critical temperature Te is then absorbed by the substrate 7 and the die 5 in the form of warpage rather than through any further planar contraction in substrate pitch and the die pitch. Also, the plurality of package solder elements 9 tend to “neck” or narrow in cross-sectional area during the misalignment, compromising both electrical and structural performance (FIGS. 1C and 1D are schematic representations of micrographs showing the “necking” problem.). As such, the prior art assembly 100 will always be necked and misaligned or skewed after a conventional reflow attachment process.
In addition, such misalignment results from the limited die placement programming currently used in the semiconductor industry. Computer-assisted design (CAD) data has been used to generate placement data from die and substrate geometries, without any regard to the thermal effects caused by reflowing the package solder onto the solder bump. Some prior art practices involve chip realignment procedures for correcting the inherent prior art misalignment at the die attachment stage of the processing (e.g., yet another solder reflow, etc.). Thus, as the die pitch (i.e., bump to bump centers) decreases, a potential for lower manufacturing yield at the flip-chip attach (FCA) stage exists due to the prior art non-variable substrate pitch configuration and to the limitations of current die placement machine tolerances. Therefore, a long-felt need exists for a method and an apparatus for preventing solder joint misalignment in the completed flip-chip assembly, rather than for merely realigning the solder joint after the reflow stage.